Interrupt Requests (IRQs) are a mechanism that allows the various devices and software that make up a computer to jump the processing queue in order to have tasks of a predetermined “higher” priority to be executed “out of turn”. BIOS services are accessed using software interrupts, which are similar to the hardware interrupts (usually generated by devices external to the CPU) except that they are generated inside the CPU by programs.

Interrupt Request (IRQ) Management

Both hardware interrupts such as those generated by I/O devices like the keyboard and mouse and software interrupts such as those generated by system software when accessing BIOS services all need to be prioritized, queued, executed and managed. Originally this was done by the CPU.

Software interrupts also make it possible for system software (DOS or the operating system), applications and other software to directly access one another via BIOS routines without having to know where the target application resides in memory.

In order to improve overall system efficiency engineers decided to create a dedicated Interrupt Request controller rather than have the CPU spend processing cycles on such a relatively simple task as I/O device interrupt request management (IRQ prioritization and queuing) and associated data transfers.

Interrupt Vector Table

Normally, to call a software routine you need to know its address (location) in memory. However; with interrupt requests a table called an interrupt vector table is created and this is used to bypass the need to explicitly know the correct address in memory. Now every time the system is booted, the BIOS puts addresses representing where its routines are located for each interrupt that it is been configured to respond to.

So whenever DOS, the operating system or other applications want to use a BIOS routine, it generates a software interrupt. The system processes the interrupt, looks up the value in the interrupt vector table and then automatically jumps directly to the appropriate BIOS routine. Modern operating systems and applications as well as DOS can also directly use this interrupt vector table.

Intel 8259 Interrupt Controller

From early on in the evolution of the PC the standard for an interrupt controller is the Intel 8259 interrupt controller. The Intel 8259 Interrupt Controller has 8 input lines (numbered IRQ0 through IRQ7) that take requests from any one of 8 different devices that are connected to it. The controller then passes the request on to the CPU informing it of which device issued the request (which device triggered the request).

Originally only one device was attached to each interrupt line. Over time as more I/O devices started to be attached to the PC the need arose for more Interrupt Request channels to become available and so a second dedicated Intel 8259 interrupt controller was added to PCs.

Cascading Interrupt Controllers

To ensure compatibility with older PCs and existing hardware the IBM AT design team didn’t want to change any of the currently existing IRQ lines that were functioning as the interrupt request highway to the CPU. Thus the decision was made to cascade the two interrupt controllers together.

The first interrupt controller still has 8 inputs and a single output going to the CPU. The second controller has the same design, but it takes 8 new inputs thereby doubling the number of interrupts.

The second interrupt controller feeds its output into input line IRQ2 of the first controller which then sends the signals to the CPU. Figure 1 below shows a logical depiction of this controller cascading arrangement. Thus; if any of the second interrupt controller’s inputs become active, the output from the second interrupt controller will trigger IRQ2 on the first controller (the big red arrow in Fig.1 below), which then signals the CPU.

Because IRQ2 was now being used to cascade the second interrupt controller motherboard designers had to change the wiring on the motherboard so that any devices which would normally have used this IRQ channel (IRQ2) were sent over to IRQ9 which is on the second interrupt request controller. In Fig 1 above device 2 is the solid red box on the right labelled DEVICE2 and as you can see it triggers IRQ9 located on the second interrupt controller.

You will also see that in Table 1 Default IRQ Allocation – By IRQ Number that IRQ2 has N/A as its priority this is because IRQ2 is used as the cascade IRQ for the second controller and is therefore unavailable for assignment to any other device.

This concept of cascading is important as system designers have reused it many times in different formats as a solution for adding additional controllers of a wide variety of types to PCs. For example; when a second DMA controller was added, designers cascaded the first DMA controller to the second DMA controller (the new one).

This arrangement meant that; unlike cascading the second interrupt controller to the first interrupt controller where rerouting of motherboard trace IRQ2 to IRQ9 was necessary, no such rerouting was required for cascading the first DMA controller to the second. You could say that the engineers had learnt from experience and improved upon the cascading system.

Interrupt Controller Chipset Integration

As has been the case with most other dedicated controllers in the PC this pair of Intel 8259 interrupt controllers have also been integrated into the system chipset on modern motherboards.

Dedicated System Interrupts

The majority of a PC’s IRQs are provided to the system bus for use by devices. However; there are 5 IRQs that are reserved for exclusive use internally by the system and are therefore not even given wires on the system buses. These dedicated system interrupts are IRQ0, IRQ1, IRQ2, IRQ8 and IRQ13.

It is also possible; in some systems, to find that additional IRQs have been reserved for internal system use. Table 1 above shows the standard IRQ channels, their default uses and parameters such as I/O Address (location in memory).

Peripheral Components Interconnect (PCI) Bus Slot Interrupts

ThePCI bus and its expansion slots use their own internal interrupt system. However; in the event of a PCI adapter card or device needing to use a regular IRQ, the system BIOS/chipset will “map” the PCI interrupt to a regular system interrupt. This is normally done using IRQ9 through IRQ12.

Maskable Interrupts

All of the various Request Interrupts mentioned above are Maskable Interrupts. This means that the CPU is able to “mask” or temporarily ignore them. The CPU will finish its current task(s) and get back to the one(s) it has postponed. Generally this state usually only occurs when an IRQ of lower priority signals the CPU for attention while the CPU is attending to other IRQs of higher priority status.

The same happens when two or more interrupts attempt to get the CPU’s attention simultaneously. In this case the IRQs are placed in a queue of descending priority which means the CPU will always attend to the IRQ of highest priority first and when finished move on to attend to the IRQ of next highest priority and so on.

Non-Maskable Interrupts (NMI)

Non-Maskable Interrupts (NMI) are used for serious conditions that demand the CPU’s immediate attention and cannot be ignored by either the system or the CPU unless the non-maskable interrupt has been specifically shut off or has been deliberately configured to be ignored. So whenever a Non-Maskable Interrupt (NMI) signal is received by the CPU it will immediately stop whatever it is doing and attend to the Non-Maskable Interrupt (NMI).

In general the Non-Maskable Interrupt (NMI) signal is normally only used for critical problem situations including serious hardware errors such as memory parity errors. Data Execute Prevention (DEP) can be considered to be a NMI because once DEP is triggered the CPU will immediately cease the relevant processing task. This is very handy when it comes to stopping malware in its tracks before it can do any damage.

IRQ Sharing and Conflicts

Interrupts are generally considered to be single device resources. Although; since the advent of the PCI bus, it is possible for devices to share an interrupt but this is not the preferred way. This is because the PCI bus has its own internal interrupt mechanisms whereas other earlier buses do not.

With devices sharing IRQs; conflicts can arise whenever you attempt to access or use two or more of the devices sharing an IRQ simultaneously. In these instances the CPU has no means by which it can explicitly identify the device that issued the interrupt request. Hence the CPU becomes confused and will subsequently issue an illegal transaction or resource conflict notification.

If you have no other choice than to configure the system with some degree of IRQ sharing then ensure that the devices that you wish to share IRQs are connected to the PCI bus. It is also advisable to only select devices that are used infrequently and never simultaneously to share an IRQ.

Plug “n” Play

Plug “n” Play is a specification that uses technology enhancements to automatically set supported devices system resources allocation and usage including IRQs, I/O Port Addresses and DMA channel assignments. In order for Plug “n” Play to work you need to satisfy the following conditions: the hardware must be Plug “n” Play compliant, your BIOS, operating system and motherboard chipset must all support the relevant Plug “n” Play standards. With these conditions satisfied by virtually all new systems today users very rarely ever need to configure IRQs themselves which is undoubtedly a good idea.

Interrupt Requests (IRQs)

When taken in combination; the assignment, issuing, management and prioritized handling of Interrupt Requests (IRQs) constitutes a computer performance enhancing technology that allows the CPU to prioritize and juggle the many processing tasks required of it. It is as a direct result of this blending approach to the processing of multiple tasks that makes the CPU appear to be doing many things at once.